1. Field of the Invention
This invention relates to an input first stage circuit, and more particularly to a current consumption reduction countermeasure for an input first stage circuit when a semiconductor device is in a standby state.
2. Description of the Related Art
Generally, an input first stage circuit of a semiconductor device is composed of a differential amplifier and several switches and has a differential amplifying action of an input signal and a current consumption reducing action when the semiconductor device is in a standby state.
An example of a conventional input first stage circuit is shown in FIG. 1(a). The input first stage circuit shown includes an differential amplifier 2a for comparing an input signal Vin with a reference voltage Vref and amplifying a voltage difference between them, a first switch circuit 8 for controlling current supply to the differential amplifier 2a, and a second switch circuit 9 for settling an output Vout of the differential amplifier 2a.
The differential amplifier 2a is a CMOS which includes N-channel MOS transistors (hereinafter referred to as NMOS) N1 and N2 to which the input signal Vin arid the reference voltage Vref are supplied, respectively, P-channel MOS transistors PMOS P1 and P2 which form a current mirror circuit, and an NMOS N4 which operates as a constant current source with a constant voltage bias supplied to the gate thereof.
The first switch circuit 8 includes PMOS P8 and P9 connected additionally to the differential amplifier 2a for stopping current supply to the differential amplifier 2a when an activation signal EB is supplied to the gates thereof. The second switch circuit 9 includes an NMOS N8 for fixing the level of the output Vout to a low level while current supply to the differential amplifier 2a remains stopped. Further, a signal S1 in FIG. 1(a) represents a gate control signal to the PMOS current mirror, a signal S4 represents a common contact signal of the differential amplifier 2a, and signals S9 and S10 represent power supply signals to the differential amplifier 2a.
An input voltage-current consumption characteristic illustrated in FIG. 1(b) indicates normalized current consumption with respect to the voltage Vin of the input signal when the input first stage circuit is active and inactive. Here, Vcc denotes a power supply voltage, Vtn a threshold voltage of the NMOS, and Vtp a threshold voltage of the PMOS. Further, a state when the voltage Vin of the input signal is lower than Vtn or falls within a range higher than a difference value (Vcc-Vtp) of the threshold voltage Vtp of the PMOS from the power supply voltage Vcc but is equal to or lower than Vcc is hereinafter referred to as standby state, that is, CMOS standby state. The standby state of a CMOS is conventionally known as a technique for reducing the current consumption of an input first stage circuit of a semiconductor device and controlling the current consumption of the entire semiconductor device to a low value, and is used widely, for example, to increase the backup time by a battery in a portable appliance and so forth.
When the activation signal EB is at the low level which indicates activation, the first switch circuit 8 exhibits an on state and differential amplifier 2a outputs a high level at the output signal Vout if the level of the input signal Vin is higher than the reference voltage Vref, but outputs a low level conversely if the level of the input signal Vin is lower than the reference voltage Vref. The current consumption however depends upon the level of the input signal Vin as seen from FIG. 1(b). More particularly, when the level of the input signal Vin is lower than the threshold value Vtn of the NMOS, the current consumption is zero, but when the level of the input signal Vin is higher than the threshold value Vtn of the NMOS, the current consumption has a current value equal to or lower than a steady current value Ia of the NMOS N4 which operates as a constant current source.
On the other hand, when the activation signal EB is at the high level which indicates inactivation, the first switch circuit 8 exhibits an off state while the second switch circuit 9 exhibits an on state. Consequently, the output Vout exhibits the low level irrespective of the level of the input signal Vin. The current consumption in this instance is zero.
In the input first stage circuit which operates in such a manner as described above, whereas the current consumption in the CMOS standby state when the Vin less than Vtn is zero, the current consumption in the CMOS standby state when Vin is greater than Vcc-Vtp is Ia. In order to reduce the current consumption, the activation signal EB is controlled to inactive, i.e., at a high level. However, when the activation signal EB should be rendered inactive depends not upon the input signal Vin but upon a different signal, and actually, the different signal is produced by a circuit which operates precedently in time to the input first stage circuit.
As a concrete example of a current consumption reduction countermeasure in such a standby state as described above, a first stage circuit formed from a general purpose DRAM for a semiconductor memory device is described.
FIGS. 2(a) and 2(b) are a circuit diagram of the input first stage circuit and a timing chart of several signals of the input first stage circuit showing details of those of FIGS. 1(a) and 1(b), respectively. The general purpose DRAM includes, as seen in FIG. 2(a), a first stage circuit 10 for an inverted row address strobe signal (hereinafter referred to as RASB signal) and a first stage circuit 11 for an inverted column address strobe signal (hereinafter referred to as CASB). The RASB first stage circuit 10 is formed from a differential amplifier corresponding to the differential amplifier 2a of FIG. 1(a) described hereinabove. Meanwhile, the CASB first stage circuit 11 corresponds to the entire input first stage circuit for current consumption reduction in the standby state of FIG. 1(a). However, the RASB is inputted in place of the activation signal EB described hereinabove.
Since the general purpose DRAM which includes the RASB first stage circuit 10 and the CASB first stage circuit 11 in this manner exhibits a standby state while the RASB signal is high as seen from FIG. 2(b), the CASB signal is varied to the low level to perform a writing/reading operation within a period within which the RASB signal has the low level. During the period during which the RASB signal is high, the first stage circuit 11 need not operate and is rendered inactive by the RASB signal so that the current consumption in the standby state is reduced. On the other hand, the RASB first stage circuit 10 does not have another signal which controls activation/inactivation of the first stage circuit 10 itself since the RASB signal makes a reference to the entire first stage circuit 10, and consequently, the current consumption of the first stage circuit 10 in the standby state cannot be reduced.
The input first stage circuit of FIG. 1(a) described above has a problem in that it requires the activation signal EB and several switch circuits which are controlled by the activation signal EB in order to reduce the current consumption in the standby state and also in that another signal for controlling the activation signal must be prepared.
On the other hand, the input first stage circuits of FIG. 2(a), particularly the RASB first stage circuit 10, has a problem in that, since the RASB signal is used as a reference signal, a signal for controlling the first stage circuit 10 to active/inactive cannot be acquired from another circuit, and consequently, such a first stage circuit which reduces the current consumption in the standby state as described above with reference to FIGS. 1(a) and 1(b) cannot be adopted. Meanwhile, the CASB first stage circuit 11 is disadvantageous in that an external activation signal such as the RASB signal is required for activation/inactivation control and that, in order to obtain such an activation signal as just mentioned, the timings with which an active period and an inactive period of the RASB first stage circuit are controlled must be designed accurately, and consequently, the CASB first stage circuit itself is complicated.